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INTEGRATED CIRCUITS
DATA SHEET
PCF8577C LCD direct/duplex driver with I2C-bus interface
Product specification Supersedes data of 1997 Mar 28 File under Integrated Circuits, IC12 1998 Jul 30
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 7 7.1 7.2 7.3 7.4 8 9 10 11 12 13 14 15 15.1 15.1.1 15.1.2 15.2 15.2.1 15.2.2 15.2.3 16 17 18 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Hardware subaddress A0, A1, A2 Oscillator A0/OSC User-accessible registers Auto-incremented loading Direct drive mode Duplex mode Power-on reset Slave address I2C-bus protocol Display memory mapping CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System configuration Acknowledge LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION CHIP DIMENSIONS AND BONDING PAD LOCATIONS PACKAGE OUTLINES SOLDERING Plastic dual in-line packages By dip or wave Repairing soldered joints Plastic small outline packages By wave By solder paste reflow Repairing soldered joints (by hand-held soldering iron or pulse-heated solder tool) DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
PCF8577C
1998 Jul 30
2
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
1 FEATURES
PCF8577C
* Direct/duplex drive modes with up to 32/64 LCD-segment drive capability per device * Operating supply voltage: 2.5 to 6 V * Low power consumption * I2C-bus interface * Optimized pinning for single plane wiring * Single-pin built-in oscillator * Auto-incremented loading across device subaddress boundaries * Display memory switching in direct drive mode * May be used as I2C-bus output expander * System expansion up to 256 segments * Power-on reset blanks display * I2C-bus address: 0111 0100. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8577CP PCF8577CT PCF8577CT PCF8577CU/10 4 BLOCK DIAGRAM DIP40 VSO40 - - DESCRIPTION plastic dual in-line package; 40 leads (600 mil) plastic very small outline package; 40 leads VS040 in blister tape chip on film-frame-carrier (FFC) VERSION SOT129-1 SOT158A - - 2 GENERAL DESCRIPTION
The PCF8577C is a single chip, silicon gate CMOS circuit. It is designed to drive liquid crystal displays with up to 32 segments directly, or 64 segments in a duplex configuration. The two-line I2C-bus interface substantially reduces wiring overheads in remote display applications. I2C-bus traffic is minimized in multiple IC applications by automatic address incrementing, hardware subaddressing and display memory switching (direct drive mode).To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD.
1 SCL I 2C - BUS 40 SDA 39 INPUT FILTERS I 2C - BUS CONTROLLER SEGMENT BYTE REGISTERS AND MULTIPLEX LOGIC BACKPLANE AND SEGMENT DRIVERS
S32
32 33 34 36 37
S1 BP1 A2/BP2 A1 A0/OSC
V DD
35 POWER ON RESET CONTROL REGISTER AND COMPARATOR OSCILLATOR AND DIVIDER
PCF8577C
VSS
38
MGA727
Fig.1 Block diagram.
1998 Jul 30
3
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
5 PINNING SYMBOL S32 to S1 BP1 A2/BP2 PIN 1 to 32 33 34 DESCRIPTION segments outputs cascade sync input/backplane output hardware address line and cascade sync input/backplane output positive supply voltage hardware address line input hardware address line and oscillator pin input negative supply voltage I2C-bus clock line input I2C-bus data line input/output
S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 1 2 3 4 5 6 7 8 9 10 PCF8577C 11 12 13 14 15 16 17 18 19 20
MGA725
PCF8577C
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
SDA SCL VSS A0/OSC A1 VDD A2/BP2 BP1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12
VDD A1 A0/OSC VSS SCL SDA
35 36 37 38 39 40
Fig.2 Pin configuration.
1998 Jul 30
4
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
6 6.1 FUNCTIONAL DESCRIPTION Hardware subaddress A0, A1, A2 6.3 User-accessible registers
PCF8577C
The hardware subaddress lines A0, A1 and A2 are used to program the device subaddress for each PCF8577C connected to the I2C-bus. Lines A0 and A2 are shared with OSC and BP2 respectively to reduce pin-out requirements. 1. Line A0 is defined as LOW (logic 0) when this pin is used for the local oscillator or when connected to VSS. Line A0 is defined as HIGH (logic 1) when connected to VDD. 2. Line A1 must be defined as LOW (logic 0) or as HIGH (logic 1) by connection to VSS or VDD respectively. 3. In the direct drive mode the second backplane signal BP2 is not used and the A2/BP2 pin is exclusively the A2 input. Line A2 is defined as LOW (logic 0) when connected to VSS or, if this is not possible, by leaving it unconnected (internal pull-down). Line A2 is defined as HIGH (logic 1) when connected to VDD. 4. In the duplex drive mode the second backplane signal BP2 is required and the A2 signal is undefined. In this mode device selection is made exclusively from lines A0 and A1. 6.2 Oscillator A0/OSC
There are nine user-accessible 1-byte registers. The first is a control register which is used to control the loading of data into the segment byte registers and to select display options. The other eight are segment byte registers, split into two banks of storage, which store the segment data. The set of even numbered segment byte registers is called BANK A. Odd numbered segment byte registers are called BANK B. There is one slave address for the PCF8577C (see Fig.6). All addressed devices load the second byte into the control register and each device maintains an identical copy of the control byte in the control register at all times (see I2C-bus protocol, Fig.7), i.e. all addressed devices respond to control commands sent on the I2C-bus. The control register is shown in more detail in Fig.3. The least-significant bits select which device and which segment byte register is loaded next. This part of the register is therefore called the Segment Byte Vector (SBV). The upper three bits of the SBV (V5 to V3) are compared with the hardware subaddress input signals A2, A1 and A0. If they are the same then the device is enabled for loading, if not the device ignores incoming data but remains active. The three least-significant bits of the SBV (V2 to V0) address one of the segment byte registers within the enabled chip for loading segment data. The control register also has two display control bits. These bits are named MODE and BANK. The MODE bit selects whether the display outputs are configured for direct or duplex drive displays. The BANK bit allows the user to display BANK A or BANK B. 6.4 Auto-incremented loading
The PCF8577C has a single-pin built-in oscillator which provides the modulation for the LCD segment driver outputs. One external resistor and one external capacitor are connected to the A0/OSC pin to form the oscillator (see Figs 15 and 16). For correct start-up of the oscillator after power on, the resistor and capacitor must be connected to the same VSS/VDD as the chip. In an expanded system containing more than one PCF8577C the backplane signals are usually common to all devices and only one oscillator is required. The devices which are not used for the oscillator are put into the cascade mode by connecting the A0/OSC pin to either VDD or VSS depending on the required state for A0. In the cascade mode each PCF8577C is synchronized from the backplane signal(s).
After each segment byte is loaded the SBV is incremented automatically. Thus auto-incremented loading occurs if more than one segment byte is received in a data transfer. Since the SBV addresses both device and segment registers in all addressed chips, auto-incremented loading may proceed across device boundaries provided that the hardware subaddresses are arranged contiguously.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
PCF8577C
CONTROL REGISTER DISPLAY SEGMENT BYTE VECTOR CONTROL (SBV) msb V5 V4 V3 V2 V1 lsb V0 0 msb
SEGMENT BYTE REGISTERS
lsb
(1)
(1) comparison
segment byte register address
2 BANK 'A' 4
6
A2
A1
A0
1
device subaddress
3 BANK 'B'
0 1
BANK 'A' BANK BANK 'B'
5
7 0 1 DIRECT DRIVE DUPLEX DRIVE DISPLAY MODE (1) Bits ignored in duplex mode.
MGA733
Fig.3 PCF8577C register organization.
OFF VDD
ON BP1
VSS VDD VSS VDD VSS 0 (VDD VSS ) 1 f
MGA737
Segment x (Sx)
BP1
Sx
LCD
Von(rms) = VDD - VSS; Voff(rms) = 0.
Fig.4 Direct drive mode display output waveforms.
1998 Jul 30
6
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
6.5 Direct drive mode 6.6 Duplex mode
PCF8577C
The PCF8577C is set to the direct drive mode by loading the MODE control bit with logic 0. In this mode only four bytes are required to store the data for the 32 segment drivers. Setting the BANK bit to logic 0 selects even bytes (BANK A), setting the BANK bit to logic 1 selects odd bytes (BANK B). In the direct drive mode the SBV is auto-incremented by two after the loading of each segment byte register. This means that auto-incremented loading of BANK A or BANK B is possible. Either bank may be completely or partially loaded irrespective of which bank is being displayed. Direct drive output waveforms are shown in Fig.4.
The PCF8577C is set to the duplex mode by loading the MODE bit with logic 1. In this mode a second backplane signal (BP2) is needed and pin A2/BP2 is used for this; therefore A2 and its equivalent SBV bit V5 are undefined. The SBV auto-increments by one between loaded bytes. All of the segment bytes are required to store data for the 32 segment drivers and the BANK bit is ignored. Duplex mode output waveforms are shown in Fig.5.
OFF / OFF VDD 0.5 (VDD VSS VDD 0.5 (VDD VSS VDD VSS VDD VSS 0.5 (VDD VSS ) 0 0.5 (VDD (VDD VSS ) VSS ) VSS )
ON / OFF
OFF / ON
ON / ON BP1
VSS )
BP2
Segment x (Sx)
BP1
Sx
VDD VSS 0.5 (VDD VSS ) 0 0.5 (VDD (VDD VSS ) VSS ) 1 f LCD
MGA738
BP2
Sx
Von(rms) = 0.791 (VDD - VSS); Voff(rms) = 0.354 (VDD - VSS). V on ( rms ) ---------------------- = 2.236 V off ( rms )
Fig.5 Duplex mode display output waveforms.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
6.7 Power-on reset 6.9 I2C-bus protocol
PCF8577C
At power-on reset the PCF8577C resets to a defined starting condition as follows: 1. Both backplane outputs are set to VSS in master mode; to 3-state in cascade mode 2. All segment outputs are set to VSS 3. The segment byte registers and control register are cleared 4. The I2C-bus interface is initialized. 6.8 Slave address
The PCF8577C I2C-bus protocol is shown in Fig.7. The PCF8577C is a slave receiver and has a fixed slave address (see Fig.6). All PCF8577Cs with the same slave address acknowledge the slave address in parallel. The second byte is always the control byte and is loaded into the control register of each PCF8577C connected to the I2C-bus. All addressed devices acknowledge the control byte. Subsequent data bytes are loaded into the segment registers of the selected device. Any number of data bytes may be loaded in one transfer and in an expanded system rollover of the SBV from 111 111 to 000 000 is allowed. If a stop (P) condition is given after the control byte acknowledge the segment data will remain unchanged. This allows the BANK bit to be toggled without changing the segment register contents. During loading of segment data only the selected PCF8577C gives an acknowledge. Loading is terminated by generating a stop (P) condition.
The PCF8577C slave address is shown in Fig.6. Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure.
S
01110100
SLAVE ADDRESS
A
MGA731
Fig.6 PCF8577C slave address.
acknowledge by all PCF8577C
acknowledge by all PCF8577C
msb
acknowledge by selected PCF8577C only
lsb
MODE
BANK
S
SLAVE ADDRESS
0A
SEGMENT BYTE VECTOR control byte
A
SEGMENT DATA
A
P
n bytes
R/W
MGA732
auto increment segment byte vector
Fig.7 I2C-bus protocol.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
6.10 Display memory mapping
PCF8577C
The mapping between the eight segment registers and the segment outputs S1 to S32 is given in Tables 1 and 2. Since only one register bit per segment is needed in the direct drive mode, the BANK bit allows swapping of display information. If BANK is set to logic 0 even bytes (BANK A) are displayed; if BANK is set to logic 1 odd bytes (BANK B) are displayed. BP1 is always used for the backplane output in the direct drive mode. In duplex mode even bytes (BANK A) correspond to backplane 1 (BP1) and odd bytes (BANK B) correspond to backplane 2 (BP2). Table 1 MODE 0 0 0 0 0 0 0 0 Segment byte-segment driver mapping in direct drive mode BANK 0 1 0 1 0 1 0 1 V 2 0 0 0 0 1 1 1 1 V 1 0 0 1 1 0 0 1 1 V 0 0 1 0 1 0 1 0 1 SEGMENT/ BIT/ REGISTER 0 1 2 3 4 5 6 7 MSB 7 S8 S8 S16 S16 S24 S24 S32 S32 6 S7 S7 S15 S15 S23 S23 S31 S31 5 S6 S6 S14 S14 S22 S22 S30 S30 4 S5 S5 S13 S13 S21 S21 S29 S29 3 S4 S4 S12 S12 S20 S20 S28 S28 2 S3 S3 S11 S11 S19 S19 S27 S27 1 S2 S2 S10 S10 S18 S18 S26 S26 LSB 0 S1 S1 S9 S9 S17 S17 S25 S25 BACKPLANE BP1 BP1 BP1 BP1 BP1 BP1 BP1 BP1
Mapping example: bit 0 of register 7 controls the LCD segment S25 if BANK bit is a logic 1. Table 2 MODE 1 1 1 1 1 1 1 1 Note 1. Where X = don't care. Mapping example: bit 7 of register 5 controls the LCD segment S24/BP2. Segment byte-segment driver mapping in duplex mode BANK(1) X X X X X X X X V 2 0 0 0 0 1 1 1 1 V 1 0 0 1 1 0 0 1 1 V 0 0 1 0 1 0 1 0 1 SEGMENT/ BIT/ REGISTER 0 1 2 3 4 5 6 7 MSB 7 S8 S8 S16 S16 S24 S24 S32 S32 6 S7 S7 S15 S15 S23 S23 S31 S31 5 S6 S6 S14 S14 S22 S22 S30 S30 4 S5 S5 S13 S13 S21 S21 S29 S29 3 S4 S4 S12 S12 S20 S20 S28 S28 2 S3 S3 S11 S11 S19 S19 S27 S27 1 S2 S2 S10 S10 S18 S18 S26 S26 LSB 0 S1 S1 S9 S9 S17 S17 S25 S25 BACKPLANE BP1 BP2 BP1 BP2 BP1 BP2 BP1 BP2
1998 Jul 30
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Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
7 CHARACTERISTICS OF THE I2C-BUS 7.4 Acknowledge
PCF8577C
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the I2C-bus is not busy. 7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. 7.2 Start and stop conditions
Both data and clock lines remain HIGH when the I2C-bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). 7.3 System configuration
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited. Each byte is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the I2C-bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'.
SDA
SCL data line stable; data valid change of data allowed
MBA607
Fig.8 Bit transfer.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
PCF8577C
SDA
SDA
SCL S START condition P STOP condition
SCL
MBA608
Fig.9 Definition of the start and stop conditions.
SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER
MBA605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig.10 System configuration.
handbook, full pagewidth
START condition SCL FROM MASTER 1 2 8
clock pulse for acknowledgement 9
DATA OUTPUT BY TRANSMITTER S DATA OUTPUT BY RECEIVER
MBA606 - 1
Fig.11 Acknowledgement on the I2C-bus.
1998 Jul 30
11
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI IDD; ISS II IO Ptot PO Tstg Note 1. Reduce by 7.7 mW/K when Tamb > 60 C. 9 HANDLING PARAMETER supply voltage input voltage on pin VDD or VSS current DC input current DC output current power dissipation per package power dissipation per output storage temperature note 1 CONDITIONS MIN. -0.5 -0.5 -50 -20 -25 - - -65
PCF8577C
MAX. +8.0 VDD + 0.5 +50 +20 +25 500 100 +150 V V mA mA mA
UNIT
mW mW C
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under "Handling MOS Devices". 10 DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; Tamb = -40 to 85 C; unless otherwise specified. SYMBOL Supply VDD IDD supply voltage supply current for non-specified inputs at VDD or VSS no load; fSCL = 100 kHz; Rosc = 1 M; Cosc = 680 pF no load; fSCL = 0; Rosc = 1 M; Cosc = 680 pF no load; fSCL = 0; Rosc = 1 M; Cosc = 680 pF; VDD = 5 V; Tamb = 25 C no load; fSCL = 0; direct mode; A0/OSC = VDD; VDD = 5 V; Tamb = 25 C VPOR Input A0 VIL(A0) VIH(A0) LOW-level input voltage HIGH-level input voltage 0 VDD - 0.05 - - 0.05 VDD V V power-on reset level note 2 - 2.5 - 50 6 125 V A PARAMETER CONDITIONS MIN. TYP.(1) MAX. UNIT
25
75
A
-
25
40
A
-
10
20
A
-
1.1
2.0
V
1998 Jul 30
12
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
SYMBOL Input A1 VIL(A1) VIH(A1) Input A2 VIL(A2) VIH(A2) VIL(SCL; SDA) Ci Output SDA IOL IL1 A2/BP2; BP1 IL2 A2/BP2 Ipd A0/OSC IL3 Oscillator IOSC LCD outputs VDC IOL1 IOH1 RBP Notes 1. Typical conditions: VDD = 5 V; Tamb = 25 C. 2. Resets all logic when VDD < VPOR. 3. Periodically sampled, not 100% tested. 4. Outputs measured one at a time. 5. Outputs measured one at a time; VDD = 5 V; Iload = 100 A. DC component of LCD driver LOW-level segment output current HIGH-level segment output current backplane output resistance (BP1; BP2) VDD = 5 V; VOL = 0.8 V; note 4 VDD = 5 V; VOH = VDD - 0.8 V; note 4 VO = VSS or VDD or 1 (V 2 SS + VDD); note 5 - 0.3 - - 20 - - 0.4 start-up current VI = VSS - 1.2 leakage current VI = VDD -1 - pull-down current VI = VDD -5 -1.5 leakage current VI = VDD or VSS -5 - LOW-level output current VOL = 0.4 V; VDD = 5 V VI = VDD or VSS 3 -1 - - LOW-level input voltage HIGH-level input voltage 0 VDD - 0.10 0 0.7VDD note 3 - - - - - - LOW-level input voltage HIGH-level input voltage 0 0.7VDD - - PARAMETER CONDITIONS MIN. TYP.(1)
PCF8577C
MAX.
UNIT
0.3VDD VDD 0.10 VDD 0.3VDD 6 7 -
V V
V V
Input SCL; SDA LOW-level input voltage input capacitance V V pF VIH(SCL; SDA) HIGH-level input voltage
mA A A A A A
A1; SCL; SDA leakage current +1
+5 - -
5 - - -0.3 5
mV mA mA k
1998 Jul 30
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Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
PCF8577C
11 AC CHARACTERISTICS VDD = 2.5 to 6 V; Tamb = -40 to 85 C; unless otherwise specified. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. SYMBOL fLCD tBS I2C-bus fSCL tSW tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO Note 1. Typical conditions: VDD = 5 V; Tamb = 25 C. SCL clock frequency tolerable spike width on I2C-bus Tamb = 25 C I2C-bus free time START condition set-up time START condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time STOP condition set-up time - - 4.7 4.0 4.0 4.7 4.0 - - 250 0 4.0 - - - - - - - - - - - - 100 100 - - - - - 1.0 0.3 - - - kHz ns s s s s s s s ns ns s PARAMETER display frequency driver delays with test loads CONDITIONS Cosc = 680 pF; Rosc = 1 M VDD = 5 V - MIN. 65 TYP.(1) 90 20 MAX. 120 100 UNIT Hz s
SCL, SDA (pins 39, 40)
1.5 k
VDD
S32 to S1 (pins 1 to 32)
6.8 k
(VDD
VSS ) / 2
MGA730
Fig.12 Test loads.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
PCF8577C
0.5 V Sx (V DD = 5 V) 0.5 V t BS VDD 2 0.5 V (V DD = 5 V) 0.5 V
MGA729
BP1, BP2
Fig.13 Driver timing waveforms.
handbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.14 I2C-bus timing diagram; rise and fall times refer to VIL and VIH. 1998 Jul 30 15
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DIRECT DRIVE LCD DISPLAY 1 32 33 64 backplane 256 S2 S1 BP1 BP2 A2 VDD Cosc R osc VSS SCL SDA VDD A1 A0 OSC VSS SCL SDA PCF8577C S31 S32 S2 S1 BP1 BP2 A2 VDD A1 A0 VSS SCL SDA PCF8577C S31 S32 OSC S2 S1 BP1 BP2 A2 VDD A1 A0 OSC VSS SCL SDA PCF8577C S31 S32
12 APPLICATION INFORMATION
Philips Semiconductors
LCD direct/duplex driver with I2C-bus interface
16
device subaddress A2.A1.A0 = 000
device subaddress A2.A1.A0 = 001
device subaddress A2.A1.A0 = 111
MGA735
Product specification
PCF8577C
Fig.15 Direct display driver; expansion to 256 segments using eight PCF8577Cs.
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BP2 DUPLEX LCD DISPLAY 1 32 33 64 BP1 128 S2 S1 BP1 BP2 VDD Cosc R osc VSS SCL SDA VDD A1 A0 OSC VSS SCL SDA S31 PCF8577C S32 A2 S2 S1 BP1 BP2 VDD A1 A0 VSS SCL SDA S31 PCF8577C S32 OSC A2 S2 S1 BP1 BP2 VDD A1 A0 VSS SCL SDA S31 PCF8577C S32 OSC A2
Philips Semiconductors
LCD direct/duplex driver with I2C-bus interface
17
device subaddress A1.A0 = 00
device subaddress A1.A0 = 01
device subaddress A1.A0 = 11
MGA736
Product specification
PCF8577C
Fig.16 Duplex display; expansion to 2 x 128 segments using four PCF8577Cs.
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
PCF8577C
32 output lines
S2 S1 BP1 BP2 VDD VDD A1 A0 VSS SCL SDA VSS SCL SDA PCF8577C S31 S32 OSC A2
device subaddress A2, A1, A0 = 000 expansion
MGA734
MODE bit must always be set to logic 0 (direct drive). BANK switching is permitted. BP1 must always be connected to VSS and A0/OSC must be connected to either VDD or VSS (no LCD modulation).
Fig.17 Use of PCF8577C as a 32-bit output expander in I2C-bus application.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
13 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
A0/OSC
PCF8577C
handbook, full pagewidth
SDA
VSS
SCL
S28
S29
S30
S31
S32
5
4
3
2
1
40
39
38
37
36 35 34 33 32
A1 VDD A2/BP2 BP1 S1 S2 S3 S4 S5 S6 S7
31 30 29 28 27 26 25
MGA726
S27 S26 S25 S24 2.31 mm S23 S22 S21 S20 S19 S18
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
x 0 0 y
PCF8577C
S17
S16
S15
S14
S13
S12
S11
S10
S9
MBE924
Chip area = 4.62 mm2. Thickness = 381 25 m. n-substrate (back) connected to VDD. Bonding pad dimensions = 110 m x 110 m.
2 mm
Fig.18 Bonding pad locations.
handbook, halfpage
Fig.19 Reference marks.
1998 Jul 30
19
S8
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
Table 3 Bonding pad locations (dimensions in m) All x and y co-ordinates are referenced to the centre of the chip, see Fig.18. PAD POSITION CENTRED SIGNAL x S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 -86 -257 -428 -599 -836 -836 -836 -836 -836 -836 -836 -836 -836 -836 -836 -836 -599 -428 -257 -86 85 256 y 941 941 941 941 941 769 598 427 256 85 -86 -257 -428 -599 -770 -941 -941 -941 -941 -941 -941 -941 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 BP1 A2/BP2 VDD A1 A0/OSC VSS SCL SDA Recpats C F -586 -580 SIGNAL x 427 598 836 836 836 836 836 836 836 836 836 836 836 836 598 427 256 85
PCF8577C
PAD POSITION CENTRED y -941 -941 -941 -770 -599 -428 -257 -86 85 256 427 598 769 941 941 941 941 941 -699 663
1998 Jul 30
20
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
14 PACKAGE OUTLINES DIP40: plastic dual in-line package; 40 leads (600 mil)
PCF8577C
SOT129-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 40 21 MH wM (e 1)
pin 1 index E
1
20
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.70 1.14 0.067 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 15.24 0.60
L 3.60 3.05 0.14 0.12
ME 15.80 15.24 0.62 0.60
MH 17.42 15.90 0.69 0.63
w 0.254 0.01
Z (1) max. 2.25 0.089
52.50 51.50 2.067 2.028
14.1 13.7 0.56 0.54
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT129-1 REFERENCES IEC 051G08 JEDEC MO-015AJ EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1998 Jul 30
21
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
PCF8577C
VSO40: plastic very small outline package; 40 leads
SOT158-1
D
E
A X
c y HE vMA
Z 40 21
Q A2 A1 pin 1 index Lp L 1 e bp 20 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.70 0.11 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 bp 0.42 0.30 c 0.22 0.14 D (1) 15.6 15.2 E (2) 7.6 7.5 0.30 0.29 e 0.762 0.03 HE 12.3 11.8 0.48 0.46 L 2.25 Lp 1.7 1.5 Q 1.15 1.05 v 0.2 w 0.1 y 0.1 Z (1) 0.6 0.3
0.012 0.096 0.017 0.0087 0.61 0.010 0.004 0.089 0.012 0.0055 0.60
0.067 0.089 0.059
0.045 0.024 0.008 0.004 0.004 0.041 0.012
7o 0o
Notes 1. Plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT158-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-24
1998 Jul 30
22
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
15 SOLDERING 15.1 Introduction
PCF8577C
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 15.3.2 WAVE SOLDERING
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). 15.2 15.2.1 DIP SOLDERING BY DIPPING OR BY WAVE
Wave soldering techniques can be used for all VSO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.3.3 REPAIRING SOLDERED JOINTS
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 15.3 15.3.1 VSO REFLOW SOLDERING
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Reflow soldering techniques are suitable for all VSO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
1998 Jul 30
23
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8577C
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Jul 30
24
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
NOTES
PCF8577C
1998 Jul 30
25
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
NOTES
PCF8577C
1998 Jul 30
26
Philips Semiconductors
Product specification
LCD direct/duplex driver with I2C-bus interface
NOTES
PCF8577C
1998 Jul 30
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/04/pp28
Date of release: 1998 Jul 30
Document order number:
9397 750 04197

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